Single-chip MCUs nearly always include some mask ROM, which is most typically used to contain critical interrupt and reset vectors and, in the case of custom MCUs, customer-supplied programs. Since, as the name implies, mask ROM is "programmed" when the masks used to fabricate the MCU are manufactured, errors in the manufacture of the masks and/or customer changes to the vectors or programs are extremely expensive to correct.
Other portions of the memory map of a single chip MCU may also be prone to expensive errors. For instance, many single chip MCUs include relatively large arrays of EEPROM and/or erasable programmable read-only memory (EPROM) which are subject to a relatively high probability of having one or more defectively manufactured locations.
Another aspect of single chip MCU operation is the need to configure the MCU to properly recognize its environment of both on-chip and off-chip peripherals and memory devices. This requires either software to continuously examine address outputs and to modify addresses to account for system configuration or some means to configure the MCU's memory map once, presumably at reset, with lasting results.
The need to patch defective or obsolete ROM by overlaying, or substituting, good memory locations is one which has long been recognized in the context of board-level memory products. For instance, U.S. Pat. No. 4,319,343 (filed July 16, 1980 and issued Mar. 9, 1982) describes a memory circuit which allows good memory to be patched over bad memory by means of programming, or setting, certain bits stored in a PROM. A portion of each address is input to the "trap" PROM, which simultaneously enables access to patch memory locations and disables the bad memory locations. The disclosed system, while suitable for a board-level memory system, is relatively too inflexible for application to an MCU, since the trap PROM is not electrically alterable and since the size of a patch block is the same as the capacity of a single memory chip. In addition, no means for implementing a patch scheme in an MCU-type environment is disclosed.
Another example of a memory patching scheme in the context of a board-level memory circuit is disclosed in U.S. Pat. No. 4,603,399 (filed Dec. 27, 1983 and issued July 29, 1986). The system disclosed substitutes certain locations in an EPROM for defective or obsolete locations in a ROM by means of a programmable logic array (PLA) which has been pre-programmed with information regarding defective or obsolete addresses. The patent discloses a means by which the size of each patch block may be efficiently varied by means of the programming of the PLA. Again, the disclosed system is effective for board-level memory products, but is not particularly suited for implementation in an MCU.
U.S. Pat. No. 4,610,000 (filed Oct. 23, 1984 and issued Sept. 2, 1986) discloses a scheme for patching a ROM which is integrated into a single package with a RAM. The system takes advantage of the fact that the control signals used to access the RAM are different from those used to access the ROM by dedicating a block of control logic to watch for addresses in the range dedicated to the ROM accompanied by control signals appropriate for RAM access. Under these conditions, the system accesses the patch ROM. This system is not useful in an MCU with a variable memory map, nor does it provide flexibility to re-configure a system such as an MCU to accommodate changing requirements.